I tried putting an Ethernet port on my own PCB for the first time and ran into a problem.
The outgoing data runs in a 100Ω differential pair (eth_TX_P and eth_TX_N) between the PHY transmitter chip at the bottom to the RJ45 jack pins (2,3) at the top. There is a signal on those lines and it looks almost right, but the signal edges are rounded and ringy. The Ethernet switch at the other end of the connection blinks like it’s seeing a signal but does not pass any data through as if it is getting and dropping corrupt packets. On my end I see the corrupted Rx packet hardware counter increasing rapidly as if I’m getting corrupt packets.
The first thing I did was change the Ethernet cable, switch port, etc. I don’t think I have any bad parts there.
The second thing I did was remove the six pin ESD protector and all of its associated capacitors from the middle of the stripline, still no luck.
Finally I started digging around on the internet and found a TI Application Note for laying out Ethernet ports. It says there should be a gap between the TX differential pair and any other top copper with a width of 3-5 times the thickness of the outer FR4 layer. What I have is shown on the right, what I think I’m supposed to have is badly photoshopped on the left. That extra capacitance may be throwing off the intended stripline impedance, causing ringing and corrupting the data.
So the question is, how do I test this assumption short of doing a whole new board spin and waiting a month for it to get back? Scrape off the soldermask with a razor and etch out the copper? Find a very nice person with a very tiny CNC? I don’t mind doing a board re-spin if I know this is really the issue, and I don’t mind putting in some manual work with the present board to make sure I have the problem solved. I guess I’m just looking for ideas on how to take off a few 10’s of mils of copper with a complex-ish shape.
Copper fills are astonishing easy to remove. You only have to cut through the copper and the soldermask with an Exacto knife around the area to remove. Then you might want to scrape off some solder mask from the copper and heat it really hot with a thick soldering tip. Pushing a little sideways should get the cut out piece of solder foil right off, as soon as the whole piece is hot enough. Sometimes you have to add some extra cuts to make the pieces smaller. See image where I would cut through first and try.
But then, looking closer at the design: I don’t know what connector you are using, but if it is a regular RJ-45 type, your signal mapping to the pins might be broken. Assuming 100baseT, normally the TX pair goes to pins 1 and 2 and the RX pair to pins 3 and 6 (or vise versa without auto-sensing). This would be much worse for your packets than a short impedance miss-match, as you are suspecting.
Thanks for the comments, I really like the idea of just cutting the copper and trying to melt off the zones you outlined. That’s much easier than trying to do a selective etch or CNC mechanical removal. I’ve accidentally removed pads that way, especially on old style PCBs by accident in the past, may as well turn that bug into a feature!
As far as the pinout goes, this is a Bel 08B0-1X1T-06-F, according to the datasheet I think I have the pin order right. The PHY isn’t reporting any polarity or Tx/Rx swap issues. The manufacturer shows the pinout as:
Yes, of course. Connectors with integrated magnetics have different pin-outs. I did not think about that.
I went and looked at the Nucleo-F429 dev board from STMicro that I used as a reference for my design. They didn’t pull back the ground plane very far from the differential Tx/Rx lines so maybe that isn’t an issue.
I did notice a big difference in the width of our traces and the spacing between the differential lines (as measured off the Gerber files):
Trace: 0.130 mm
Trace: 0.290 mm
Space: 0.140 mm
An oddity of my board is that the outer layers are 2oz copper since this processor shares a PCB with some high current components. I calculated out the stripline impedance as shown below.
The calculated width and spacing (W and S in the Physical Parameters) box look close to what I measured on the board, and the expected differential impedance is right at 100Ω as expected.
Unfortunately I can’t find enough data on the Nucleo-F429 board’s stackup to do a comparison calculation.
I’ll see if I can find a known working design with Gerbers and stackup data and see if their parameters give me a 100Ω stripline or if I’m using this calculator tool wrong.
Those pesky calculators. Just out of interest I punched the numbers into my goto calculator, the Saturn PCB tool and here is the result:
The only difference I found is that 2oz copper is 0.07mm but that does not make a hugh difference, I also tried the KiCAD calculator.
Still I would assume a mismatch for such a short trace should not break your system, especially on the inside of the transformer. I have done much worse things to USB3 pairs and they were very robust.
Your best bet is probably a decent scope with differential or 2 high speed probes and look at the signals, if they are distorted or not.
Thanks for checking that impedance calc! If I understand you correctly, we got somewhat different impedance estimates but not likely far enough off to cause a major issue over a ~1cm long line.
I unfortunately don’t have proper differential probes, so I took two traces with some 10x probes and set the PHY to 10Mbit mode to make the signals slower. I also fed the PCB clock from one channel of a function generator and recorded a 10MHz square wave from the other channel, both originate from the same oscillator so they should be phase locked. Then I dumped the scope data into a file to analyze on my PC.
If I understand 10Mbit/s encoding the differential Tx signal (green) should be getting read every time the clock (blue) has a negative edge. Then at the start of the Ethernet frame there should be 7 sync bytes worth of 0xAA, aka 0b10101010, followed by a start-of-frame delimiter byte of 0xAB. Let’s see what we got:
The first byte looks good, but then the first nibble of the second byte is 0xF instead of 0xA as expected. Well, that certainly does change things. I thought the PHY auto-generated the SYNC/SOF for me, but it’s not outputting what it should? I’m out of time for playing with this today, but it looks like maybe the PCB is fine and I have some research to do into where this bit pattern came from.
Thanks for your help and pushing the investigation off into new directions!