There's always a worse package to break out

Unless you’re the PCB engineer breaking out the M3…

12 Layer board with blind vias to every layer. Wonder what the per unit cost on the PCB inside an iphone runs? What does the economy of scale look like on a highly advanced PCB like that?

Without counting, I think there are more pins in that package than the first Apple II’s RAM had in bits.

That is a really interesting thought. I just had to check.

According to wikipedia, which is never wrong about anything, Apple I and II default to 4KB RAM. So maybe not as many pins as bits, but as many pins as RAM addresses seem pretty feasible. It’s definitely not far off.

Apple 1 has 256B ROM so I’d definitely bet M3 has more pins than Apple 1 had ROM bits.

Yeah, I have no idea about the M3’s “pin” count. But 4,096 seemed low, so I went for bits instead of bytes.

Here is a package that is a pain to break out for totally different reasons, the IXTK200N10L2 N-channel linear MOSFET:


It’s a high current device so you need to get a wide copper trace onto the drain and source pins. The source pin is no problem since it’s on the side of the device, just make a trace as wide as the pin is long if you want to. The drain, however, is the center pin so you have to bring in a wide trace from the other side, via it down to another layer, and then via it back up under the drain pin.

Just making the gate the center pin would make this thing so much easier to use!

What is the Tab connected to? If its Drain you can just do a small trace connecting the lead to the tab pad?


Ok the Tab is connected to the drain, so you shouldn’t need to have to draw all the current through the drain pin if you bend it over and connect the tab.

But yeah this is a fairly unusual layout for the high power fet.

What is the Tab connected to? If its Drain you can just do a small trace connecting the lead to the tab pad?

You can do that at low currents, but that device can conduct 60A+ and dissipate ~300W so mounting it on the PCB would result in fire.

When I used it the device was hanging off the edge of the board on a big water-cooled heatsink along with several other power components operating at different voltages. Everything needed an electrically insulating thermal pad, so using the tab as a terminal was a no-go.

I completely overlooked that, wonder why they designed the package in that way. Wonder if something with the die made moving the gate to the middle pin uneconomical / impossible?

Probably because it works better with the vertical construction of power mosfets. [1] VDMOS is a somewhat old structure, so this part is likely not using it exactly, but it’s certainly some type of vertical (not planar) construction. That also means many of the rules of thumb one normally uses for small signal transistors don’t necessarily apply to this part.

[1] Power MOSFET - Wikipedia