Circuit Break Podcast #430: The Toilet Mountain of Social Media

Podcast Title: The Toilet Mountain of Social Media

Release Date: 2024-05-10

Episode: #430

In this episode, Parker Dillmann and Stephen Kraig delve into the hefty topic of U.S. funding for ‘digital twin’ chips research under the CHIPS Act, comparing its budget to other big expenditures like Boeing’s Starliner and military budgets. They also discuss EDA tool pricing, breaking down costs from freeware to industry heavyweights, and the implications for small vs. large businesses. Additionally, Parker shares his personal project update on his first KiCad PCB.

Podcast Audio:

Podcast Notes:

Key Discussion Points

  • Introduction to the topic of U.S. funding for ‘digital twin’ chips research and its comparison to other large expenditures.
  • Overview of the CHIPS Act, its budget, and its place in the broader U.S. budget context.
  • Discussion on the price and subscription models of various EDA tools, from entry-level to high-end industry standards.
  • Analysis of the impact of EDA tool pricing on small businesses versus large corporations.
  • Parker’s personal project update: success with his first KiCad PCB.
  • The hosts reflect on the social dynamics of Twitter and its impact on public discourse and political polarization.
  • Discussion about the complexities of U.S. political funding and its transparency.
  • Comparison of software subscription models and their financial implications for users.
  • Reflections on the interaction between engineering, politics, and social media.

Relevant Links

Community Questions

  • What are your thoughts on the use of ‘digital twin’ technology in chip manufacturing?
  • How do you think the costs associated with EDA tools affect startups and small businesses?
  • Do you have any personal experiences with the challenges of using subscription-based vs. perpetual license software?

The “digital twin” thing is a weird nomenclature. I’m pretty sure it’s just describing co-simulation which is a standard feature in most, if not all RTL simulators. Here’s how one can do it in Verilator or VCS for RISCV RTL (ok technically it’s Chisel but it is the RTL gets simulated).

It shows how to get GDB to attach to the simulator and one can look into their git repo to see how the harness works. It’s fairly straightforward.

I guess maybe they want to glue more EDA tools together into the environment. Or maybe they’re looking to improve the performance of that connection? If that’s the case, give those guys $500 million. :slight_smile: