Will have to dig more into this but the pricing looks almost reachable for hobbiests. Definitely in the realm for startups!
As I recall from four years ago, it was free if your chip was selected to go on the wafer (and that was likely). Then Matthew Venn started a subproject where he would subdivide one of the wafer slots into 4x4 (and eventually progressed to 10x10?) and people could put small designs into those.
Unfortunately, Google ended the free shuttle program in 2023.
However, Matt continues to offer an affordable way to learn how to develop an IC and then get them manufactured through efabless. (The same company that worked with Google.)
A shuttle design means there is a pre-defined block (a RISC-V MCU) with an area available to add your custom design. So far, people have made very interesting chips!
That is an interesting concept. Allowing you to roll your own custom peripherals.
I heard Google’s original intent was to provide a pipeline for more ASIC designers. I wonder if they have a follow-on effort or if they decided the program wasn’t working.
I like the TT idea. Certainly the price is good ($150 for earlybird). But there are caveats:
- Circuit size of about 1000 gates for a single tile. (Although you can buy additional tiles for $50.)
- Eight inputs, eight outputs, and an eight-bit bidirectional bus.
- Approximately a year between design submission and receiving your chip.
- I’m not sure how many chips you get with TT other than the one mounted on the board. (I know with the Google program you got a bucket of chips.)
This would be a great program if I was doing some type of analog ASIC. For a digital design, they could just send me a demo board with an FPGA and a serial PROM and I wouldn’t know the difference.
Tiny Tapeout works well in conjunction with Matt’s Zero to ASIC course. The focus of that program is teaching how to design a chip and give you experience in the workflow.
It is a fun idea for the experience. But it isn’t going to be the starting point of the next TI.
Especially with how inexpensive smaller fpgas have gotten over the years.
Still I agree with James that it would be a fun experience to learn. I took one chip layout class and I don’t remember much of it anymore.
Given that, you probably won’t remember what your chip does once you get it!
What did I eat for lunch?
That’s more or less true. Person behind a lot of these efforts from Google is a friend of mine. He’s been pushing on open-source tooling for FPGAs and ASIC design for quite some time.